1. Technical Field
The present invention relates to a switching device and a testing apparatus. More particularly, the present invention relates to a switching device that connects or disconnects, to/from each other, a drain electrode and a source electrode provided on a semiconductor layer and to a testing apparatus using the same.
2. Related Art
Patent Document 1 discloses a mechanical relay using a reed switch surrounded by a metal guard pipe. The mechanical relay achieves excellent high-frequency characteristics since the guard pipe and the reed switch are arranged coaxially. Patent Document 2 discloses an photo MOSFET relay. The photo MOSFET relay is a semiconductor relay and thus has a longer lifetime than a mechanical relay. Patent Document 3 discloses a semiconductor relay that is turned on/off in such a manner that a high voltage is applied to a control gate to inject electrons into a floating gate and that a gate portion is irradiated with an ultraviolet ray to cause the electrons to be emitted.
A testing apparatus for performing a logic test on a device under test (DUT) includes a pin driver that outputs a test signal to the DUT and a pin comparator that detects an output signal output from the DUT. In order to be capable of performing a direct current (DC) test as well as the logic test, the testing apparatus additionally includes a DC test unit that outputs a DC voltage, a relay (an I/O relay) that connects and disconnects the DUT to/from the pin driver and the pin comparator, and a relay (a DC relay) that connects and disconnects the DC test unit to/from the DUT. The I/O relay and the DC relay are mechanical relays or photo MOSFET relays, for example.
[Patent Document 1] Japanese Patent Application Publication No. 2004-185896
[Patent Document 2] Japanese Patent Application Publication No. 10-294488
[Patent Document 3] Japanese Patent Application Publication No. 03-208409
A mechanical relay provides electrical connection and disconnection by opening and closing of a metal contact. Therefore, the metal contact deteriorates due to friction and the like. Accordingly, the mechanical relay has a short lifetime. Furthermore, the mechanical relay cannot be integrated into a semiconductor integrated circuit, which results in a large size and undermines efforts to increase the device density.
A photo MOSFET relay is configured such that components such as a photocell, alight emitting diode, and a MOSFET are mounted on a lead frame and connected to each other by means of bonding wires. Therefore, the photo MOSFET relay is complex in structure, large and expensive. In addition, the photo MOSFET relay exhibits poor high-frequency characteristics because of the parasitic inductances of the lead frame, bonding wires and the like and the RC product of the on resistance and the gate capacitance of the MOSFET. Furthermore, since the photocell and the light emitting diode are formed by using a GaAs semiconductor or the like, the photo MOSFET relay cannot be integrated together with other circuits that are formed by using a silicon semiconductor. For the reasons stated above, the photo MOSFET relay hampers attempts to reduce the size of a device including the photo MOSFET relay, to increase the density of the device and to lower the cost of the device.
According to the semiconductor relay disclosed in Patent Document 3, it is required to irradiate the gate portion with an ultraviolet ray to cause the electrons to be emitted. The semiconductor relay thus cannot be easily turned on/off.
Here, the testing apparatus outputs a test signal having a high frequency such as several GHz. Accordingly, it is desirable that the I/O relay is capable of transmitting a high-frequency test signal with low distortion and transmitting a test signal whose frequency widely ranges from a DC to approximately several 10 GHz with a low loss. In the testing apparatus, it is desirable that the impedance of the transmission path between the pin driver and the DUT accurately takes a predetermined value (for example, 50Ω). Accordingly, the I/O relay desirably has a small number of impedance mismatch points. Furthermore, the I/O relay desirably has a low DC on resistance so that the loss and waveform distortion can be prevented.
The DC relay is connected at one end thereof to the DUT-side terminal of the I/O relay. Therefore, when the testing apparatus performs a logic test, the electrostatic capacitance of the DC relay during the off state is added to the impedance of the transmission path between the pin driver and the DUT. For this reason, the DC relay desirably has a low electrostatic capacitance during the off state in order to reduce its influence on the impedance of the transmission path for a logic test. Furthermore, the DC relay desirably has a low DC on resistance such that there is no difference in DC level between the output end of the DC test unit and the input end of the DUT.
Here, the testing apparatus repeatedly performs tests, which indicates that the I/O relay and the DC relay are turned on/off a very large number of times. Therefore, the I/O relay and the DC relay desirably have a long lifetime.
In light of the above, a switch that is utilized as the I/O relay in the testing apparatus desirably has excellent high-frequency transmission characteristics, a wide frequency range and a low loss, a small number of impedance mismatch points, and a low DC on resistance. On the other hand, a switch that is utilized as the DC relay in the testing apparatus desirably has a low electrostatic capacitance during the off state and a low DC on resistance. Furthermore, the switches that are utilized as the I/O relay and the DC relay in the testing apparatus desirably have a long lifetime. Here, the mechanical relay and the photo MOSFET relay discussed above both have advantages and disadvantages for their usage as the I/O relay and the DC relay in the testing apparatus.